Recently, as design rules for semiconductor devices are decreased and the semiconductor device is integrated, a SOI structure has attracted considerable attention as a way to reduce junction capacitance between a silicon substrate and junctions by providing an insulator between the silicon substrate and semiconductor devices.
In a SOI substrate having the SOI structure, isolation is achieved by employing a silicon oxide film as an insulation film. Therefore, in case that the SOI substrate is used in a semiconductor field, it is possible to prevent soft errors and/or a latch up phenomena to improve reliability of the semiconductor device. Further, because the junction capacitance of the impurity diffuse layer of active regions can be reduced in case of an integrated circuit having the SOI structure, the amount of charge and discharge current due to switching decreases, resulting in reduced power consumption.
The SOI substrate is, however, more expensive than the typical silicon substrate. Further, fine defects may be generated in the insulation film of the SOI substrate, thereby deteriorating the yield of the semiconductor device.
In order to solve the problems, a study of a method for fabricating a SOI structure in a logic process has been conducted. Referring to FIGS. 1A to 1D, there are provided schematic cross sectional views setting forth a prior approaches for fabricating shallow trench isolation(“STI”).
The prior method begins with the preparation a silicon substrate 1. As shown in FIG. 1A, an oxide layer is deposited on the silicon substrate 1 as a first insulation layer 2 and a nitride layer is deposited thereon as a second insulation layer 3. Next, on the second insulation layer 3 are formed photoresist patterns 4 serving to a mask by applying and patterning photoresist thereon.
Referring to FIG. 1B, portions of the second insulation layer 3 uncovered with the photoresist patterns 4 are removed by a dry etching to partially expose the first insulation layer 2. Subsequently, thus exposed portions of the first insulation layer 2 are removed by a dry etching till the silicon substrate 1 is partially exposed therethrough. Next, thus exposed portions of the silicon substrate 1 are etched in a predetermined thickness by a dry etching to form trenches 5.
Referring to FIG. 1C, the photoresist patterns 4 are removed and then cleaning is performed. Next, a gap filling is carried out on the trenches 5 by using trench filling material to form a trench isolation layer 6. Thereafter, a chemical mechanical polishing is performed to remove a portion of the trench isolation layer 6 covering the top surface of the second insulation film 3 to form trench isolation films 7 (see FIG. 1D), thereby producing a shallow trench isolation (“STI”) structure where the trench isolation films 7 are disposed in only the trenches 5, i.e., non-active regions.
Thereafter, the second insulation layer 3 used in establishing STI structure are removed by a wet etching and then semiconductor devices are formed by various processes, e.g., an ion implantation.